Intel has confirmed in its 42nd Edition of Instruction Set Extensions and Future Programming Reference that the Sapphire Rapids-SP succeeding Ice Lake-SP in 2022 will include support for on-package HBM2 memory. Considering that the Aurora Supercomputer leveraging Ponte Vecchio and Sapphire Rapids will make use of HBM memory as a cache of sorts, it’s possible that we’re looking at an intermediary cache between the CPU and GPUs or the CPU and DRAM.
The 15th Chapter includes machine error codes for Sapphire Rapids-SP, with Section 15.1 mentioning the error codes for integrated memory controllers of these processors. The interesting bits are the error codes for HBM command/address parity errors and HBM data parity errors, indicating that Sapphire Rapids will be compatible with HBM memory.
Sapphire Rapids is going to be Intel’s biggest leap in performance and feature-set, boasting a new core architecture, a further refined version of the 10nm node, PCIe 5.0, CXL 1.1, DDR5 memory, and the latest Optane technology. The Golden Cove architecture will bring support for the more complex 512-bit instructions such as Advanced Matrix Extensions (AMX) as well as AVX512_BF16 and AVX512_VP2INTERSECT which are important for Data Center and AI-based workloads.
Sapphire Rapids is expected in early 2022, with samples shipping to select clients by the end of 2021.
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Title: Intel’s Sapphire Rapids-SP to Support on-package HBM2 Memory
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Published Date: Thu, 31 Dec 2020 14:55:56 +0000